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 Post subject: Four AMD Bulldozer Chips Incoming
 Post Posted: Fri Mar 18, 2011 4:56 am 
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http://www.xbitlabs.com/news/cpu/display/20110313113629_Four_AMD_Bulldozer_Chips_Incoming_Details_Revealed.html

and

http://www.xbitlabs.com/news/cpu/display/20110313163718_AMD_Aims_to_Fight_Core_i7_Sandy_Bridge_with_Bulldozer.html

Quote:
With its FX-series AMD Zambezi desktop processors the Sunnyvale, California-based company plans to fully compete against Intel Core i-family of high-performance central processing units. A document from AMD seen by X-bit labs claims that AMD FX-series central processing unit (CPUs) powered by the Bulldozer micro-architecture will be fully able to rival Core i7 2600-series chips.


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 Post subject: Re: Four AMD Bulldozer Chips Incoming
 Post Posted: Sat Mar 19, 2011 6:19 am 
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Location: same place as before :)
Quote:
Four chips are not a large number and they will hardly be able to properly compete against rather huge Intel Core i7-series microprocessors, which includes quad-core and six-core offerings. But this - initial offering by AMD - may not be the "army" to attack Intel, but rather than a lineup to show what AMD is capable of: creation of a competitive high-end microprocessor. The second breed of Bulldozer-based chips due in Q4 is supposed to really improve AMD's positions on the market of expensive central processing units. By the end of the year AMD, based on a document seen by X-bit labs, expects approximately 10% of its CPUs to be FX-series in AM3+ form-factor.

AMD Orochi design is the company's next-generation processor for high-end desktop (Zambezi) and server (Valencia) markets. The chip will feature eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one "Flex FP" floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have shared L3 cache, new dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Zambezi chips will use new AM3+ form-factor and will require brand new platforms.


gimme :)

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